EDN

FPGA-to-ASIC conversion a crucial concern

It is clear that FPGAs are great for prototyping and low-volume production. It's also clear, however, that any relatively complex mid- to high-volume design for which power consumption, component cost ...
Business Wire

Faraday Unveiled FPGA-Go-ASIC Prototyping Platform to Accelerate FPGA-to-ASIC Conversion

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today unveiled its FPGA-Go-ASIC™ prototyping platform solution. This ...
EDN

FPGA-prototyping and ASIC-conversion considerations

The capacity and capability of modern FPGAs support the implementation of many digital systems, making FPGAs the platforms of choice for developing, prototyping, and deploying digital logic. Depending ...
Semiconductor Engineering

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

Digital systems need clocks. Today’s designs require more from clocking schemes than ever before, and it’s likely this trend will continue. Increasing power constraints have resulted in finer-grained ...
AV Network

Justin Kennington on AV Supply Chain Using FPGA vs. ASIC Chips

SDVoE Alliance President, Justin Kennington shares his perspective on how FPGA versus ASIC chips impacts the product supply chain in the AV industry. When you purchase through links on our site, we ...
Hackaday

Your Own Open Source ASIC: SkyWater-PDK Plans First 130 Nm Wafer In 2020

You might have caught Maya Posch’s article about the first open-source ASIC tools from Google and SkyWater Technology. It envisions increased access to make custom chips — Application Specific ...
Electronic Design

ASICs, Structured ASICs, And FPGAs

How close in performance and integration are FPGAs and ASICs? Advances in FPGA architectures and the use of 90-nm process rules have allowed the latest generation of FPGAs to achieve levels of ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Digi Times

FPGA vs ASIC: Altera CEO highlights FPGA's advantage in AI era

Embedded World 2025 officially commenced this week in Nuremberg, Germany, with Sandra Rivera, CEO of FPGA company Altera, delivering the keynote address. In her presentation, Rivera discussed key ...
Electronic Design

JESD204B Converters Simplify FPGA And ASIC Interfacing

It isn’t unusual for an analog-to-digital converter (ADC) to be Electronic Design’s Best Analog product of the year, particularly when its performance characteristics are remarkable. Yet in this case, ...
Semiconductor Engineering

The FPGA Alternative

Until a few years ago, SoC designers focused almost exclusively on ASICs. While it was theoretically possible to create an SoC design for an FPGA, the programmable chips were too bulky and pricey to ...