EDN

Using bit-error-rate testers to test-drive FEC codes

FEC (forward error correction), a critical component of many modern digital-communications applications, turns otherwise-unusable links into real and practical ...
Electronic Design

Test & Measurement: Powerful Bit-Error-Rate Tester Works At 1500 Mbits/s

The BA1500 1500-Mbit/s BitAlyzer bit-error-rate (BER) tester provides detailed BER tests and points out where and when errors occur. It shows errors, block errors, and error-free interval statistics ...
EDN

Bit-error-rate tester exposes jitter completely

Said to be the only instrument to offer complete jitter tolerance testing for the highest-speed digital interfaces, the J-BERT N4903B serial bit-error-rate tester lets engineers accurately ...
Electronic Design

Bit-Error-Rate Testers Face Ethernet Speed Challenges (.PDF Download)

Bit-Error-Rate Testers Face Ethernet Speed Challenges (.PDF Download) July 20, 2016 ...
Semiconductor Engineering

A Machine-Learning-Resistant 3D PUF with 8-layer Stacking Vertical RRAM and 0.014% Bit Error Rate Using In-Cell Stabilization Scheme for IoT Security Applications

Multi-layer 3-dimensional (3D) vertical RRAM (VRRAM) PUF with in-cell stabilization scheme to improve both cost efficiency and reliability. The proposed PUF features excellent resistance against ...
HotHardware

Cadence Demos Optical PCIe 7 Connection At A Blistering 128GT/s

The 2024 PCI-SIG Developers Conference, or "SIG DevCon", took place last week, and one of the most impressive demos on the show floor was undoubtedly Cadence's. The company demonstrated PCIe 7.0 ...